| 摘要 |
<p>PURPOSE:To switch two types of clock signals CLK with different phases and frequencies without generating glitch and waveform abnormality by providing a means to detect the phase of a clock signals, and to confirm that the clock signal becomes at a low level when the clock signal is switched. CONSTITUTION:When a Q output of a flip flop FF2 becomes at 1, an AND 8 gate is turned on, a CLKA becomes enable, further, the CLKA passes through an OR 10, and is produced as an output 17. Next, when a switching signal becomes at 0, the Q output of an FF3 becomes at 1 at the fall point of the CLKA, the Q output of an FF1 is at 0, the Q output of an FF4 is at 1 at the falling point of a CLKB, and the Q output of the FF2 is at 0 at the next falling point of the CLKA. Consequently, since the Q output of the FF2 is at 0 at the AND 8, the gate is turned off, and when the level of the CLKA is completely changed from a High 1 to a Low 0, the gate is switched. For this the CLKA is switched without being cut off in the middle or generating the glitch.</p> |
