| 摘要 |
<p>A dynamic memory circuit which can operate at a high speed and with a reduced amount of noise is disclosed. The memory circuit includes word lines and a pair of dummy word lines arranged in rows, a plurality of bit line pairs arranged in columns, a plurality of memory cells, dummy capacitors connected between the dummy word lines and the bit line pairs and a plurality of transfer gate pairs inserted between the bit line pairs and the sense amplifiers.</p> |
