| 摘要 |
PURPOSE:To reduce the area of a memory cell, and to improve the degree of integration by connecting one end side of a conductive layer to one semiconductor region in a MISFET for transfer and connecting the other end side of the conductive layer onto the top face of a gate electrode for a MISFET for drive. CONSTITUTION:A memory cell M is constituted on the main surface of a p-type well region 4B. One semiconductor region 16 in a MISFETQt for transfer and a gate electrode 10A for a MISFETQd for drive are connected, and a high- resistance load element R connected to the connecting section, interposing a conductive layer 20A is composed of a memory cell M arranged to the upper section of the MISFETQd for drive. A connecting area is reduced only by a section corresponding to the quantity of displacement of mask alignment in manufacturing processes between both one semiconductor region 16 in the MISFETQt for transfer and the gate electrode 10A for the MISFETQd for drive at the time when both the semiconductor region 16 and the gate electrode 10A are connected directly, and the degree of integration can be improved. |
