发明名称 LOGIC CIRCUIT
摘要 A logic circuit includes an inverter circuit including a first enhancement type field effect transistor having a gate connected to an input, and a first depletion type transistor having a gate and a source which are directly connected to a drain of the first enhancement type field effect transistor. A source follower circuit including a second enhancement type field effect transistor having a gate is connected to a connecting point of the first enhancement type field effect transistor and the first depletion type field effect transistor. A second depletion type field effect transistor having a gate and a source which are directly connected to each other has a drain which is connected to a source of the second enhancement type field effect transistor. A first power source is connected to the drains of the first depletion type field effect transistor and the second enhancement type field effect transistor and a second power source is connected to the sources of the first enhancement type field effect transistor and the second depletion type field effect transistor. An output is formed at the connecting point of the second enhancement type field effect transistor and the second depletion type field effect type transistor.
申请公布号 DE3569859(D1) 申请公布日期 1989.06.01
申请号 DE19853569859 申请日期 1985.12.24
申请人 FUJITSU LIMITED 发明人 TAKAO, HISOKA;SATO, TOSHIRO;SAITO, SEIICHI;HAYASHI, TOSHINARI
分类号 H03K19/0944;H03K19/0952;(IPC1-7):H03K19/094 主分类号 H03K19/0944
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