发明名称 PIPELINE TYPE SLAVE PROTOCOL FOR HIGH PERFORMANCE CPU-EPU CLUSTER
摘要 PURPOSE: To improve CPU capacity by making it possible to recover CPU status information only when the result of an executed floating point instruction is exceptional. CONSTITUTION: A shadow storage means storing the additional information related to the status of a CPU 10 at the time when the executions of a floating point instruction and an integer instruction are overlapped and the time corresponding to the issue of the floating point instruction to a floating point device 12 is provided within the CPU 10. The additional status information is capable of recovering the contents of a CPU register when the result of the execution of the floating point instruction is exceptional. Except the case of the exception, the advancing of the CPU 10 to the execution of the next integer or the floating point instruction is allowed. Thus, the CPU 10 is capable of obtaining high capacity.
申请公布号 JPH01140330(A) 申请公布日期 1989.06.01
申请号 JP19880228290 申请日期 1988.09.12
申请人 NATL SEMICONDUCTOR CORP <NS> 发明人 SORIN IAKOBOBITSUCHI
分类号 G06F7/00;G06F9/38 主分类号 G06F7/00
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