| 摘要 |
In an A/D converter in which a first comparator A/D converter for providing the most significant bits of a digital output and a second comparator A/D converter for providing the least significant bits of the digital output are cascaded, a switching circuit is provided between the first A/D converter and the second A/D converter. This switching circuit is responsive to the comparison between an analog input voltage and first comparison reference voltages in the first A/D converter to apply two adjacent first reference voltages between which the analog input voltages lies to both ends of a voltage dividing circuit network of the second A/D converter to thereby provide second comparison reference voltages. In the second A/D converter, the second comparison reference voltages are compared with the analog input voltage by comparators, to provide the least significant bits of a digital output. |
