| 摘要 |
<p>The system comprises an analog integrated circuit using integrated field effect transistor technology comprising a plurality of sampling and storage cells (20). To achieve the high speed performance required, a two-stage sampling cell design is used. The first stage (22) incorporates a very small capacitor (C1) coupled to the input signal through a high speed gate (Q1, Q3). This gate, which is opened only by the simultaneous occurrence of row and column signals, causes their first capacitor (C1) to capture at very high speed a sample of the analog signal under study. When all the first capture sections (22) of the cells have captured on their capacitors (C1) a sample of the analog signal, a transfer gate (Q7) is briefly opened to transfer the captured and buffered sample values to a second or storage section (24) of the cells (20). This storage section (24) incorporates a capacitor (C2) substantially larger than the capacitor (C1) in the capture section (22), and capable of storing the signal for a considerably longer time.</p> |
