发明名称 |
Charge disturbance resistant logic circuits utilizing true and complement input control circuits |
摘要 |
A cross-coupled load logic gate family which will keep voltage at a logic gate output below that of a switching threshold and a subsequent logic gate during a charge disturbance upset.
|
申请公布号 |
US4833347(A) |
申请公布日期 |
1989.05.23 |
申请号 |
US19880144664 |
申请日期 |
1988.01.12 |
申请人 |
HONEYWELL, INC. |
发明人 |
RABE, ROBERT L. |
分类号 |
H03K3/356;H03K19/003;H03K19/0948 |
主分类号 |
H03K3/356 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|