MULTIPROCESSOR SYSTEM ARCHITECTURE

摘要

A multiprocessor system architecture in which at least two processors are provided each with an autonomous bus and the two busses can be selectively connected to each other to constitute a unique system bus and enabling access to common memory resources connected to an autonomous bus by all the processors. The processor communication takes place through messages stored into "mailboxes" included in the common memory resource and the presence of a message is evidenced by notify/interruption signals generated by a logic unit to which each processor has access to modify and verify its status, using its autonomous bus, without interfering with the operations running on the other autonomous busses and without requiring access to common memory resources and polling operations for verifying the pending status of messages into "mailboxes".