NON VOLATILE SEMICONDUCTOR MEMORY

摘要

PURPOSE:To enable any data to be written in an avalanche region where a higher program efficiency is assured by defining the gradient of a load line upon write operation substantially by resistance. CONSTITUTION:A resistor R is serially inserted between a power supply UP and a load transistor 104, the resistor R is serially inserted between a transistor 104 and a row select transistor C1, and the resistor is serially inserted between a memory cell BL1 and the row select transistor C1. The resistor R is serially inserted between the power supply VP and the drain of the memory cell and set to dominantly define a load line. There is no need of completely defining the load line only by the resistor R. That is, the resistor R may relax the characteristics of a current ID changing in the square with respect to a change 'VG-VIH'' of a MOSFET. Accordingly, for load resistance by the MOSFET and the load resistance R by polysilicon or a diffusion layer, the latter may be set to be larger.