| 摘要 |
PURPOSE:To quicken the pull in of phase, by controlling the selection of a selector at the interruption of an input clock, and presetting the 2nd frequency division circuit at re-input. CONSTITUTION:A pseudo phase difference signal generating circuit comprising a decoder 42 generating a phase pulse oscillating a voltage controlled variable frequency oscillator 35 near the center frequency and a flip-flop 37, is provided. The generating circuit is controlled with a phase difference pulse outputted from the pseudo phase difference signal generating circuit at the interruption of input clock and runs itself near the center frequency. The 2nd frequency divider 31 is preset so that the output pulse phase of the 2nd frequency divider 31 frequency- dividing the input clock at the re-input of the clock is started from almost the same phase as that of the output signal of the pseudo phase difference signal generating circuit. Thus, the pull-in range is extended to the lock range and quick pull-in of phase is attained. |
