| 摘要 |
<p>PURPOSE:To decrease the capacity of a frame aligner to one frame by using a clock extracted from a data so as to apply synchronizing processing of a multi-frame. CONSTITUTION:A CRV signal extracted from the multi-frame by a multi-frame counter circuit 1 is used to write a signal representing a number corresponding to each frame to the idle bit of an input data in a frame aligner 3 via a shift register 2 by one frame each. The frame data written in the aligner 3 is read by a frame counter circuit 4 operated by a system clock and the signal representing the number corresponding to the frame is extracted by a shift register 5 and the readout data is processed by a status processing section 6. Moreover, the data itself is sent to the succeeding device. Thus, the capacity of the frame-aligner 3 is constituted by one frame.</p> |
