| 摘要 |
PURPOSE:To obtain MIS transistor structure, which is offset gate structure and reduces source resistance, by disposing a gate, one end section thereof is positioned onto the end section of a shallow second one conductive type region and the other end onto an other conductive type region separate from a drain region. CONSTITUTION:The N<+> type drain region 6 having a one conductive type, a deep N<+> type source region 5 of the first one conductive type region and a source region consisting of a shallow N<+> type source region 7 of the second one conductive type region, which is formed to a side surface approaching to the drain region 6 and is shallower than the source region 5, are formed separately to an element forming region surface obtained by isolating and exposing the surface of an Si substrate 1 of the other conductive type such as a P type by a field oxide film 2. A gate electrode 4, one end section thereof is positioned onto the end section of the shallow source region 7 and the other end thereof onto the P type region separate from the drain region 6, is disposed onto the P type region between the shallow source region 7 and the drain region 6 through a gate oxide film 3. An offset region 1b, to an upper section thereof the gate electrode is not placed, is formed between the N<+> type drain region 6 and a lower region of the gate electrode 4. |
