Data transmission system between a main CPU board having a wait signal generating latch and a plurality of CPU boards

摘要

A data transmission system between a main CPU and a plurality of sub-CPU's includes a data bus connected between them, a CPU select line for transmitting a CPU select signal from the main CPU to the sub-CPU's, a latch circuit for providing a wait signal to the main CPU upon write or read in the main CPU with respect to the sub-CPU's and a wait clear line connected between the respective CPU's to provide to the latch circuit a wait clear signal upon completion of input and output of the sub-CPU to release the waited state of the main CPU, the transmission system being thereby simplified to reduce installation space and wiring labor.