| 摘要 |
PURPOSE:To improve current driving capacity of a logic circuit and to make it possible to use a conventional wiring software by providing a cell region of which unit cell is formed by use of a complementary insulating gate effect transistor and by providing a wiring channel region having an additional field effective transistor in a part whereof. CONSTITUTION:A cell region 1 of which unit cell 3 is formed by use of a complementary insulating gate field effect transistor is provided to compose a gate array. Additional field effective transistors 4, 5 are provided in a part of a wiring channel region 2, alternately with the cell region 1 to make connection between unit cells 3. For instance, in the wiring channel region 2, an N channel MOS transistor 4 and a P channel MOS transistors 5a, 5b are additionally formed before a primary Al wiring layer 6 which is wired crosswise and a secondary Al wiring layer 7 which is formed lengthwise through an interlayer insulation film are provided. The transistor 5b is connected in paralleled to a transistor of the added side of the unit cell when the secondary Al wiring layer 7 is formed. |
