| 摘要 |
PURPOSE:To eliminate noise with a higher probability by inputting respective delaying signals of plural signal delaying circuits to two logical circuits and setting and resetting the FF with the output of these logical circuits. CONSTITUTION:When an input signal I1 is inputted to a signal delaying circuit 4 composed of delaying circuits 1 and 2, signal delaying output signals DL1 and DL2 of different signal delaying time (TDL1, TDL2) are outputted from the circuits 1 and 2. The signals DL1 and DL2 and the input signal I1 are inputted to input AND circuits 2 and 3 and an input NOR circuit 3, an FF 5 is set by the output of the circuit 2 and the FF 5 is reset by the output of the circuit 3. At this time, even when the noise is mixed into an input signal I1 at the same time interval as the delaying time TDL1 or TDL2, the FF 5 is not set or reset by the noise, therefore, the above-mentioned noise is not outputted to the Q output of the FF 5. |
