| 摘要 |
<p>The memory comprises a plurality of individually activatable rows (Rn) and a plurality of main columns (C1, C2) which cross said rows and are connected, at each crossing corresponding to a logical "0", to a pull-down cell (N1) controlled by the crossed line, each main column leading to the supply voltage through a respective pull-up transistor (P1, P2). According to the invention, an auxiliary column (CX1, CX2) is associated with each main column and is also connected to the supply voltage through a respective pull-up transistor (PX1, PX2), and is connected, at each crossing corresponding to a logical "1", to a pull-down cell (P2) controlled by the crossed line; the gates of the pull-up transistors of the main columns are connected to the auxiliary columns, and the gates of the pull-up transistors of the auxiliary columns are connected to the main columns.</p> |
