Bi-CMOS semiconductor device immune to latch-up

摘要

A circuit including a Bi-CMOS semiconductor device of a structure capable of preventing the latch-up phenomenon from occurring when operated as an inverter or the like. The semiconductor device includes a MOS FET and a bipolar transistor merged with each other and having a PNPN or NPNP structure in a region to which minority carriers can migrate through diffusion and in which a same potential is applied to at least a pair of P-type and N-type regions or a backward voltage is applied across PN junctions in operation. The semiconductor device comprises electrodes provided in both P-type and N-type regions, respectively, which form one of the PN junctions, wherein a backward voltage not lower than 0.5 V is applied across the electrodes upon operating the device.