| 摘要 |
A vertical, enhancement mode InP MISFET includes a conducting n-type substrate, a semi-insulating Fe-doped InP blocking layer on the substrate, a conducting layer formed in the blocking layer, a groove which extends through both the conducting layer and the blocking layer, a borosilicate dielectric layer formed on the walls of the groove, a gate electrode formed on the dielectric layer, drain electrodes formed on each side of the gate electrode, and a source electrode formed on the bottom of the substrate. When a positive gate voltage relative to the source is applied, conduction channels are formed along the sidewalls of the groove, and current flows vertically from drain to source.
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