| 摘要 |
<p>PURPOSE:To simplify a data input circuit and to minimize a chip size by storing the selection of bytes in a load period and respectively outputting 'VPP' in an automatic deletion period and '0' in a write period. CONSTITUTION:Y address selecting FET-QY1,1 and Qg1 are driven by Y address line Y1 and the like in common. Column latch circuits CL1,1-CL32.8 are provided with byte latch circuits BL1-BL32 between gates Qg1-Qg32 and a deletion voltage VPPE1, and data input FET-QIN1-QIN8 in node points SC1-SC8. A deletion voltage YPPE3 supplied to the latch circuits CLi and BLi come to 'VCC' in the load period, 'VPP' in the automatic deletion period and '0' in the write period, and a load signal LOAD supplied to the gate of QIN comes to 'VCC' only in the load period. In the activation of a load signal line, write data is latched into a latch circuit corresponding to a selected digit line.</p> |
