发明名称 SENSE AMPLIFIER CIRCUIT FOR SEMICONDUCTOR MEMORY
摘要 <p>PURPOSE:To alter the rate of currents flowing in a memory cell and a dummy cell by connecting enhancement N-type FETs and depression N-type FETs in serial. CONSTITUTION:The depression N-type FET-D2, D3, D4 and D5 which have respec tively ion-implanted are connected with enhancement N-type FET-N2, N3, N4 and N5 in serial. Thus, the rate of the currents flowing in the memory cell and the dummy cell can be altered to 1/3. On the other hand, the current rates of respective cells become 1/2 when ion-implantation is not executed on D5, but on D2-D4.</p>
申请公布号 JPH0198195(A) 申请公布日期 1989.04.17
申请号 JP19870255833 申请日期 1987.10.09
申请人 NEC CORP 发明人 KOBAYASHI MASAHIRO
分类号 G11C7/00;G11C11/34;G11C11/419;G11C16/06;G11C17/00;G11C17/18;H03K5/08 主分类号 G11C7/00
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