发明名称 VERTICAL MOS TRANSISTOR AND MANUFACTURE THEREOF
摘要 PURPOSE:To prevent a punch-through current, to abruptly rise VG-IDS characteristic, and to prevent thermal runaway by forming a region to which a concentration first conductivity type impurity lower than the impurity concentration of a second conductivity type well layer and higher than the impurity concentration of a first conductivity type semiconductor substrate in the well layer on a substrate. CONSTITUTION:A P-well region 21 is formed on an N-type semiconductor substrate 1, and an N-type impurity region 25 having higher impurity concentration than that of an N-type region 1b and lower impurity concentration than that of the region 21 is formed at a position in contact with N<+> type source regions 4a, 4b in the region 21. In a channel region 24, since the N-type impurity of the region 25 is higher than that of the region 1b but lower than the P-type impurity concentration of the region 21, its conductivity type is of P-type. The peak of the P-type impurity concentration near the source end of the region 21 is reduced, and the gradient of the impurity concentration becomes substantially flat.
申请公布号 JPH0196962(A) 申请公布日期 1989.04.14
申请号 JP19870255323 申请日期 1987.10.08
申请人 NISSAN MOTOR CO LTD 发明人 YAO TAKEYUKI
分类号 H01L29/10;H01L29/78 主分类号 H01L29/10
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