High-speed overlapping window register file.

摘要

A combination of elements provide support for communication of arguments between routines in an instruction processing apparatus. This combination includes a register file comprising a set of addressable registers. A first sub-set of the registers and a second sub-set of the registers define a pluarlity of register pairs. Each register pair includes a respective one of the registers in the first sub-set and a respective one of the registers in the second sub-set. Sub-set allocating means are provided having a first state for allocating the first sub-set as a group for incoming arguments and the second sub-set as a group for outgoing arguments, and a second state for allocating the second sub-set as a group for incoming arguments and the first sub-set as a group for outgoing arguments. Register-access control means enables each of successively invoked routines to access all the registers that define the register pairs and includes register-selecting means for supporting a predetermined type of instruction, which predetermined type of instruction contains a state-independent reference for use in forming an address to select a register. The register-selecting means includes address-altering means controlled by the sub-set allocating means for swapping the addresses of the two registers of each register pair to enable communication of arguments between calling and called routines without inter-register transfers of arguments.