发明名称 |
FORMATION OF SELF-ALIGNED STACKED CMOS STRUCTURES BY LIFT-OFF |
摘要 |
<p>A process for fabricating a self-aligned three-dimensionally integrated circuit structure having two channel regions responsive to a common gate electrode. A relatively thick lift-off region is formed over and in alignment with the gate electrode. A thick oxide layer is then deposited over the structure so as to form stressed oxide extending from the lift-off layer sidewalls. A selective etch of the stressed oxide follows. The relatively thick oxide covering the lift-off layer is then removed with the etch of the lift-off layer, the lift-off etch acting through the exposed lift-off layer sidewalls. The formation of an upper field effect transistor gate oxide and a conformal deposition of polysilicon for the channel and source/drain regions follows. The conformally deposited polysilicon retains the contour of the recess formed by the lift-off. The gate aligned recess is then filled with a dopant masking material by deposition and etching, which dopant masking material thereafter defines during implant or diffusion an upper field effect transistor channel region self-aligned with the common gate electrode, The characteristics of the upper field effect transistor can be improved by applying laser recrystallization techniques.</p> |
申请公布号 |
CA1252222(A) |
申请公布日期 |
1989.04.04 |
申请号 |
CA19870539208 |
申请日期 |
1987.06.09 |
申请人 |
NCR CORPORATION |
发明人 |
SZLUK, NICHOLAS J.;MILLER, GAYLE W. |
分类号 |
H01L27/00;H01L21/822;H01L21/8234;H01L21/8238;H01L27/06;H01L27/088;H01L27/092;H01L29/78;H01L29/786;(IPC1-7):H01L21/82 |
主分类号 |
H01L27/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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