DIGITAL PEAK-HOLD CIRCUIT

摘要

A digital peak-hold detector for determining the peak value of an input analog voltage to be displayed on a multiple-element display device detects when the value of the input analog voltage exceeds the value of a ramp-like waveform generated from a counter which repetitively counts down from a number equal to the total number of display elements to zero to generate a compare signal. A control circuit strobes the count corresponding to the peak value into a storage register when the value of the input analog voltage exceeds the current peak value in the storage register. A digital comparator compares the current peak value from the storage register with the repetitive count from the counter and outputs an update signal when the value of the count is greater than the current peak value. The update signal is combined with the compare signal by the control circuit to make the determination whether to update the current peak value. A time delay circuit causes the control circuit to clear the storage register to generate a new peak value when the current peak value is not updated within a predetermined period of time.