Method of and circuit arrangement for ensuring bit synchronization of a data block in a receiver

摘要

For synchronizing a data block in a receiver, there are transmitted consecutively and prior to the data block: a first bit sequence of alternating "0" and "1" levels for determining the bit clock and a second bit sequence for determining the block synchronization by correlation. In known methods of determining the bit clock, the phase range of the individual bits of the received digital signal is divided into sub-intervals and the phase position of the bit clock is determined on account of the number of edges in these sub-intervals. In order to avoid fading and phase jitter having a detrimental effect on the bit synchronism, more specifically when transmitting through radio transmission links, N-phase-shifted clocks having the same clock frequency are generated in the receiver by means of which the first bit sequence is sampled. The clock for which the number of sample-value changes of the first bit sequence is established as having a predeterminable minimum value during a predeterminable time-interval is utilized as the phase synchronous bit clock.