发明名称 DIGITAL TRANSMISSION DATA REGENERATING CIRCUIT
摘要 PURPOSE:To regenerate transmission data without depending upon a data transmission rate by generating a bit synchronizing signal and a character synchronizing signal from a two-phase signal accompanying a transmission data signal. CONSTITUTION:An (n)-bit shift register 12 is initialized with a character start synchronizing signal 15 and regenerates the transmission data signal inputted to an input terminal 13 in sequence by using a bit synchronizing signal 14 as a shift clock. At the same time, a counter 17 which is reset with a character start synchronizing signal 14 counts the bit synchronizing signal 14 to count character bits. An R-S flip-flop 26 is reset with the character start synchronizing signal 15 and set with a character end synchronizing signal 22. Consequently, a regenerated data output 16 and a character count output 18 are read correctly.
申请公布号 JPS6481425(A) 申请公布日期 1989.03.27
申请号 JP19870239609 申请日期 1987.09.22
申请人 NEC CORP 发明人 UEDA TSUGIO
分类号 H04L7/04;H04L7/08;H04L25/38 主分类号 H04L7/04
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