发明名称 SYSTEM FOR CONTROLLING INTERRUPTION
摘要 PURPOSE:To improve the operating efficiency of a system by decreasing the generation of a DMA over-run, preventing the over-run from concentrating to the same channel and decrease the number of tries based on it. CONSTITUTION:The titled system provides a CPU1, a storage device 2, plural I/O devices and plural channel devices 3 to control the I/O device by a command from the CPU1. This is an interruption control system in an information processing system, in which the I/O device can directly execute the transmission and reception of information through the device 3 with the device 2. In this system, plural interrupting signals are prepared from the respective devices 3 to the CPU1. When the over-run of the input and output device is detected in an ending interruption request in direct information transferring between the I/O device and the device 2 by the command from a firmware, out of plural interrupting levels signals, a switching a executed to the interrupting level of a highly priority and interruption is requested again.
申请公布号 JPS6476248(A) 申请公布日期 1989.03.22
申请号 JP19870232492 申请日期 1987.09.18
申请人 FUJITSU LTD 发明人 YAMAGUCHI TATSUYA;TANAKA NOBUO
分类号 G06F13/12;G06F13/24 主分类号 G06F13/12
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