| 摘要 |
PURPOSE:To prevent a chip size from becoming large by a method wherein a power supply is fed to a circuit-element formation layer from a conductive layer through a substrate of a first conductivity type and a region of the first conductivity type. CONSTITUTION:A metallized layer 53 is formed nearly on a whole face of a stage 52 of a package 51, and is connected to package leads 54 of a power supply VEE. The power supply VEE is supplied to a semiconductor chip 50 via the package leads 54 and the metallized layer 53, and is supplied to an ECL circuit and the like via first-layer wiring parts 31 and a second-layer wiring part 32 from a p<+> type substrate 41, a p<+> type layer 44 and an n<+> type isolation layers 24. During this process, because wiring parts 58 of a small area for power supply use are dispersed, wiring parts can be installed between them and can be used as signal wiring parts; a degree of freedom of the signal wiring parts is enhanced sharply. Because the potential VEE can be supplied from the rear of the chip, the wiring parts required to distribute the VEE can be made very short. |
