发明名称 SERIAL/PARALLEL CONVERSION SYSTEM FOR SIGNAL
摘要 PURPOSE:To contrive the reduction of the number of wires, by transmitting a data signal and a clock signal and power supply through one and the same line from a control circuit, extracting the signals at the reception circuit side and generating the power supply. CONSTITUTION:A control section 10, a parallel serial conversion means 101, a clock signal generator 102, a signal conversion means 103, and a controlled section 11 are provided and a start bit section 12, a conversion section 13 and a succeeding similar conversion section are used. Moreover, the titled system is provided with an output drive power generating means 122, circuit stabilized power supply generating means 121, 131, a start signal detection means 123, a signal extracting means 132 extracting a clock signal and a data signal, a signal distribution means 133 comprising 2-stage of flip-flop circuits, latch means 134, 135 for a data signal, a next stage start signal generating means 137, and output means 138, 139. Then the controlled section separates and extracts the clock signal and the control signal superimposed on a serial signal from the signal line to output a parallel control signal.
申请公布号 JPS6472623(A) 申请公布日期 1989.03.17
申请号 JP19870229978 申请日期 1987.09.14
申请人 KURODA PRECISION IND LTD;NAKAMURA KIKI ENG:KK 发明人 NAKANISHI KOJI;SAITO YOSHITANE
分类号 F16K31/06;H03M9/00;H04L25/38 主分类号 F16K31/06
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