发明名称 SYSTEM FOR CONTROLLING LOW ORDER DEVICE
摘要 PURPOSE:To speed up an interrupting processing without imposing a big burden on a low-order central processor by providing a signal line for transmitting an interrupting signal from a low-order device to the low-order central processor to a bus adapter part between the low-order device and the bus adapter part. CONSTITUTION:The signal line 7 for transmitting the interrupting signal transmitted from the low-order device 6 to the low-order central processor 5 to the bus adapter part 3 between the low-order device 6 and the bus adapter part 3. Consequently, the interrupting signal from the low-order device 6 is appropriately processed by the command of the high-order central processor 1 and the like according to whether the high-order central processor 1 or the low-order central processor 5 has instructed of starting even if the low-order central processor 5 does not judge the device which has instructed of starting. Thus, the interrupting processing can be executed without imposing the big burden on the low-order central processor 5.
申请公布号 JPS6473447(A) 申请公布日期 1989.03.17
申请号 JP19870229762 申请日期 1987.09.16
申请人 FUJITSU LTD 发明人 INESHIMA SHINJI;KAGEYAMA MASAHISA;OI YASUSHI;YOKOMIZO SHINICHI;TAKESHITA JUNKO
分类号 G06F13/12;G06F13/24;G06F13/36;G06F15/16;G06F15/173;G06F15/177 主分类号 G06F13/12
代理机构 代理人
主权项
地址