发明名称 LOGIC CIRCUIT
摘要 <p>PURPOSE:To reduce the power consumption by holding a potential at an output terminal to a low potential when no logic circuit is employed so as to reduce the current flowing to a load resistor. CONSTITUTION:The logic circuit comprises a NAND circuit 3, a load resistor R, a power supply -V and an unconnected device display means 2. The means 2 consists of a flip-flop or the like and when a circuit connected to the logic circuit at the pre-stage exists, an output 12 is kept to a logic value '1' (low potential). Thus, when the circuit is not in use, a logical '1' (low potential) always appears at the output terminal O of the NAND circuit 3, the current flowing to the load resistor R is reduced.</p>
申请公布号 JPS6468125(A) 申请公布日期 1989.03.14
申请号 JP19870226111 申请日期 1987.09.09
申请人 NEC CORP 发明人 TAKANASHI SHUICHI
分类号 G06F1/32;H03K19/00;H03K19/0175;H03K19/086 主分类号 G06F1/32
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