发明名称 LEVEL CONVERSION CIRCUIT
摘要 <p>PURPOSE:To set optionally a hysteresis width by turning on/off in response to the magnitude relationship between the 1st and 2nd reference voltages and the voltage at the output terminal, changing the 2nd reference voltage and supplying a current to the output terminal in case of the ON-state. CONSTITUTION:When a resistor, e.g., R8 is connected to one terminal of the 1st switching means Q4 as the voltage means and an output of the reference voltage generating means R5, R6 and the 1st switching means Q4 is turned off, since the current flowing to the voltage change means R8 is zero, the voltage drop is zero and the 2nd reference voltage is identical to the 1st reference voltage. when the 1st switching means Q4 is turned on, however, since the current flowing thereto flows the means R8, the 2nd reference voltage is higher than the 1st reference voltage (or lower) by the voltage drop. Thus, the transition point of the voltage when the output voltage rises is VA2, but the transition point when the output voltage is decreased is VA3. Thus, the hysteresis width is smaller than the increase/decrease width Vh.</p>
申请公布号 JPS6467027(A) 申请公布日期 1989.03.13
申请号 JP19870223714 申请日期 1987.09.07
申请人 AISIN SEIKI CO LTD 发明人 HATAKEYAMA AKIRA;KIMURA NOBUYASU
分类号 H03K19/0175;H03K3/2893;H03K5/02;H03K19/00 主分类号 H03K19/0175
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