| 摘要 |
The multiplexer apparatus for multiplexing four low-speed bit streams into a single high-speed bit stream comprises: a buffer memory (5) of which one unit is provided for each of the four-low speed bit streams, for temporarily storing the four-low speed bit streams; a reference clock pulse generator (1) for generating a reference clock pulse for the operation of the multiplexer apparatus; a pulse generator (2) for frequency-dividing the reference clock pulse by a predetermined number and generating read and write clock pulses for the buffer memory (5), the pulse generating means being capable of varying the bit rates of the read and write clock pulses in response to the bit rates of the low-speed bit streams; and a multiplexer (10) responsive to the read clock pulse for multiplexing the four low-speed bit streams read out of the buffer memory (5) into the high-speed bit stream. The multiplexer apparatus realizes in a single apparatus both a second order MUX apparatus and a third order MUX apparatus conforming to the CCITT Recommendations G.742 and G.751, respectively. A corresponding demultiplexer is also provided. |
