| 摘要 |
The adder circuit according to the subject of the invention differs from the adder circuit according to P 3717504.1 mainly in that the main circuit 2 consists only of five AND circuits 9, each with two inputs, and five OR circuits 10, each with two inputs. This simplification is made possible by the double use of input e 4, which is either not triggered with high potential, or only triggered with high potential by the output of AND circuit 20 via OR circuit 19, or only triggered with high potential by the carry output n of the dual full adder 6 via OR circuit 19. <IMAGE>
|
