发明名称 |
Error correction coding and decoding circuit for digitally coded information. |
摘要 |
<p>An error correction coding and decoding circuit for digitally coded information in which a majority difference set cyclic code is used to apply error correction coding and decoding to a data signal having data bits suitably assigned to information bits and parity bits, characterized in that a clock signal (CLKC) for the internal operation of the circuit, a data load clock signal for loading data onto the circuit, and a data read clock signal for reading data from the circuit are delivered from an external circuit provided separately from the error correction coding and decoding circuit.</p> |
申请公布号 |
EP0306020(A2) |
申请公布日期 |
1989.03.08 |
申请号 |
EP19880114279 |
申请日期 |
1988.09.01 |
申请人 |
NIPPON CONLUX CO., LTD.;NIPPON HOSO KYOKAI |
发明人 |
YAMAZAKI, KOICHI;KIMURA, YASUYUKI;YAMADA, OSAMU;KURODA, TORU |
分类号 |
H04L1/00;H03M13/00;H03M13/33;H03M13/43 |
主分类号 |
H04L1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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