| 摘要 |
<p>A delay type flip-flop arrangement using transistor-transistor logic receives a clock signal (CP) and input data (D) and outputs a logical output (Q) in accordance with the logic level of the data. The arrangement includes a master flip-flop (1) for transmitting a change in the logic level of the data to a pair of output ends (N1, N1) when the clock signal is at a predetermined logic level; a slave flip-flop (2) for latching the data transmitted via the pair of output ends; an output buffer (3) for effecting a buffering of the data latched in the slave flip-flop; and a drive circuit (4) for driving the output buffer. The drive circuit responds to logic levels of data (Q1, Q1) appearing at the pair of output ends of the master flip-flop and, based on the logic levels, drives the output buffer to determine the logic output (Q) to be output from the arrangement. This reduces the total propagation delay time and realises a high speed operation without increasing the power dissipation.</p> |
