| 摘要 |
PURPOSE:To quickly transmit and receive data by directly transferring data between each processing module and an objective module in the same manner as data transfer between the module and a main memory by the DMA (direct memory address) control of a DMA controller. CONSTITUTION:Only when the DMA request from a module whose response is indicated by a first mode register means 14 is received by a DMA controller 10, a main memory M1 responds to the DMA control of the controller 10. When the DMA request from a data transfer destination designated by a third mode register means 16A is accepted by the DMA controller 10, modules A1, B1... output prepared data onto a bus at the DMA operation timing of the controller 10 and issue the DMA request in response to the report of data preparation completion from a data transfer source designated by a second mode register means 15A. Thus, data is quickly transferred. |
