| 摘要 |
PURPOSE:To shorten the time required for the collation of a doubled controlling part and the detection of inconsistency and to prevent an incorrect output at the time of inconsistency, by making impossible traffic among four controlling parts consisting of microprocessors respectively each other through a data transfer bus. CONSTITUTION:Input/output controlling parts 1, 3 read necessary data from an input part 6 and store the data in respective internal memories. The data are transmitted to arithmetic controlling parts 2, 4 through the data transfer bus 40. The controlling parts 1, 3 receive the operated results from the controlling parts 2, 4 through the bus 40 and store the received data in the internal memories to collate both calculated results. When both results coincide with each other, the value is outputted to an output part 8 as the newest calculated result. At the time of inconsistency, the collation processing is repeated and the internal defective state of the controlling parts 1, 2 is outputted to the external as an alarm to obtain a normal system output automatically by selecting and controlling an output switching part 9. |
