APPARATUS AND METHOD FOR SELF-RISTRICTION OF ERASING MEMORY CELL USING FLOATING GATE

摘要

PURPOSE: To self-limit the electrical erasure of a single transistor floating gate EEPROM cell by making a control gate additionally positive as well for the purpose of feeding back from a drain to a gate and similarly coupling the floating gate to positive. CONSTITUTION: A substrate 21 is grounded during an erasing operation. An erasing potential (VERASE) is then impressed on a source 23 and an amplifier 30 is coupled between the gate 22 and the terminal 28 of the control gate 27. The gain of the amplifier 30 is carefully adjusted, by which the correct feedback voltage is impressed on the terminal 28 with an increase in the drain potential during the erasing operation and the positive voltage in the floating gate 27 is coupled via the floating gate 26. As a result, a tunnel process decreases with the increase in the positive potential at the floating gate 26 until finally the tunnel process is stopped before the cell is put into the supererased state. As a result, the disabling over the entire part of the array by the supererased state does not arise and the self-limitation of the electrical erasure of the single transistor floating gate cell is made possible.