| 摘要 |
PURPOSE: To raise the yield of a multi-chip module by processing multi-level interconnection lines, separated from a multi-chip module and bonding them to this module after completing the process. CONSTITUTION: A polyimide layer 18 is formed on an oxide layer 16 grown in an Si wafer 14, a metal layer 20 is deposited to form specified interconnection lines, a polyimide layer 24 is formed including vias 26 extending to the metal layer 20, and a metal layer 28 is deposited and patterned. These steps are multiply repeated to deposit a final metal layer, this layer is patterned to form a final polyimide layer 32, and an oxide layer 16 is etched to separate the multi-level interconnection lines from the wafer 14. These interconnection lines are aligned and bonded to a multi-chip module, and vias are etched, metallized, and patterned to connect dies of the module to the multi-level interconnection lines. This reduces the chance of breakdowns.
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