| 摘要 |
PURPOSE:To attain high reliability, by exchanging a command signal with a response signal, through a bus which is provided between multiple operation processing devices to which plural processing means are connected, and synchronizing the taking-in of input data and taking-out of output data. CONSTITUTION:Input data 1 is processed by clocks 8 and 9 incorporated in CPUs 6 and 7 to become outputs 2 and 3; and if they coincide with each other in an AND circuit 4, they are sent as an output 5 to a circuit which is not shown in Fig. A bus 10 is provided between CPUs 6 and 7, and the CPU6 transmits a command signal C1 to the CPU7 at intervals of a certain period. The CPU7 returns a response signal R1 immediately when receiving the signal C1, and the CPU7 sends the output to the AND circuit 4 after the transmission time of the signal R1 from the CPU7 to the CPU6 elapses, and the CPU6 sends the output to the AND circuit 4 immediately when receiving the signal R1. If one CPU is faulty, it is reported to the other by a signal line 11, and the other CPU performs the operation processing independently outputs the output. Thus, data take-in and out are synchronized accurately with a simple device to attain high reliability. |
