| 摘要 |
PURPOSE:To realize the memory control of both a direct memory access controller (DMAC) and a CPU with no distinction given between them, by providing a conversion means which maps plural logical addresses into a single physical address. CONSTITUTION:A mask page table (MPT) 7 is set in a memory control mechanism (MMU) 6 to define the logical addresses of a DMAC 5 as a table of page units. Then the logical addresses are inputted to the MMU 6 from a CPU 1 and the DMAC 5 via address buses a1 and a2. Thus the logical address of the DMAC 5 is entered to a page table 9 in a memory 8 and the logical address of the DMAC 5 is entered to the MPT 7 respectively. In a DMA transfer the MMU 6 refers to the contents of the table 9 and the MPT 7 and judges whether the physical addresses to which the CPU 1 and the DMAC 5 try to give accesses are equal to each other or not. If so, the priority is given to the MPT 7 and the access to the CPU 1 is kept waiting. Thus the accesses to the same area can be avoided. |
