发明名称 CLAMP CIRCUIT
摘要 PURPOSE:To attain small sized circuit and stable operation by providing a differential amplifier whose one input terminal receives an input signal, two MOS gates of the same structure connected in series, a reset means discharging the electric charge of the storage capacitance at the start of clamping, a current source, a charge flowing control means and a feedback means feeding back the potential of the storage capacitance to the input terminal. CONSTITUTION:Suppose that an applied pulse phiB is at a low level at a point of time t3, then the electric charge exists in the deeper potential well in MOS gates 14, 15. Then the potential well is made shallower and the potential is reduced while the charge flows to the storage capacitor 17. The potential is fed back to a differential amplifier 13 via a level shifter 20. When the depth of the potential well under the MOS gates 14, 15 is made nearly equal and balanced, then the charge is thrown away in the dray through the potential well under the MOS gate and the clamping is finished. When the pulse phiB reaches a high level at a time t4, the charge is thrown away in the drain through the gate 19. Thus, even with the fluctuation of an output Vout, the storage capacitance is not caused and stable clamping is attained.
申请公布号 JPS6436215(A) 申请公布日期 1989.02.07
申请号 JP19870192070 申请日期 1987.07.31
申请人 TOSHIBA CORP 发明人 GOTO HIROSHIGE
分类号 H03K5/007;H04N5/18 主分类号 H03K5/007
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