| 摘要 |
PURPOSE:To increase the working speed of an I<2>L for a bipolar CMOS integrated circuit by simultaneously forming one conductivity type first region as one part of an emitter in an inverter transistor for the I<2>L and one conductivity type second region as a well in a MOS transistor. CONSTITUTION:An N<+> type well region 7a as one part of an emitter region in an inverter transistor for an I<2>L and an N<+> type well region 7b in a P channel transistor for a CMOS are shaped simultaneously, thus improving the performance of both the I<2>L and the CMOS. That is, emitter concentration just under a base region 8 is increased, the injection efficiency of the inverter transistor can be enhanced and the storage of hole charges in an epitaxial layer can be reduced by forming the N<+> type well region 7a in concentration higher than the epitaxial layer 4 in an I<2>L section. Accordingly, the fT of the inverter transistor is augmented, and tpdmin can be made small, and the working speed of the I<2>L can be increased. |
