发明名称 CONTROL SYSTEM FOR PERFORMANCE OF COMPUTER
摘要 PURPOSE:To ensure the correction of the performance control error, the improvement of reproducibility and the suppression of variance of the instruction executing time, by stopping a counting action of a computer with an interlock signal. CONSTITUTION:The performance of a computer is controlled in a computer system where a pipeline is controlled by a microprogram. In this case, a correcting counter IPC13 is added when an interlock signal is energized. Thus the performance errors produced with misshits are counted by the counter IPC13 with the interlock signal. Then the counting action of a main performance control counter 11 is stopped for a period of time equal to a corrected extent after the end of a memory access.
申请公布号 JPS6423345(A) 申请公布日期 1989.01.26
申请号 JP19870180555 申请日期 1987.07.20
申请人 FUJITSU LTD 发明人 FUJIOKA SHUNTARO;FUJIMAKI HIDEAKI;TORIKAWA KUNIHIRO
分类号 G06F9/38;G06F11/22 主分类号 G06F9/38
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