| 摘要 |
PURPOSE:To speed up data transfer between drives by executing the DMA transfer of data through drive controllers. CONSTITUTION:An AND gate 5 is connected to synchronizing DMA request signals DRQ1, DRQ2 from the drive controllers 2A, 2B with each other and the output of the gate 5 is inputted to a DMA controller 1. A source address (the address of a transferring source), a destination address (transferred address), etc., are set in the DMA controller 1 from an external register or the like. Then, the status of drive controllers 2A, 2B is checked, and after confirming that both the controllers 2A, 2B are in a ready state, commands are outputted to respective controllers 2A, 2B. Thereby, a READY command is applied to the controller 2A and a WRITE command is applied to the controller 2B. Consequently, data transfer between the drives 3A, 3B can be speeded up. |
