| 摘要 |
<p>PURPOSE:To make it unnecessary to provide a delay gate specially as a delay circuit, and to test a circuit at timing, close to an actual operation by providing the delay circuit consisting of an RC time constant circuit for delaying a control signal in an output buffer. CONSTITUTION:The control signal F is delayed by the delay circuits 1-m, constituted of the RC time constant circuits consisting of resistors R between the respective output buffers OB1a-OBma and capacitors C. Accordingly, when the control signal F, the pulse width of which is shorter than delay time, is outputted, the output buffers can be made to operate successively in order from the output buffer OBma to the output buffer OB1a. Thus, it comes unnecessary to provide the delay gate specially as the delay circuit, and circuit constitution comes simple, and in addition, the delay time can be made shorter, and the circuit can be tested at the timing, close to the actual operation.</p> |
