| 摘要 |
PURPOSE:To restrain the generation of level of III-V compound semiconductor/ insulating film boundary, by constituting a second semiconductor layer formed on a first semiconductor layer, of group III-V compounds, making group V element forming the second semiconductor layer identical with group V element in the first semiconductor layer, and making the energy gap of the second semiconductor layer smaller than that of the first semiconductor layer. CONSTITUTION:On a p-type GaAs epitaxial layer 12 formed on, e.g. an semiinsulative GaAs substrate 11, an InAs intermediate layer 13 is formed, on which a CaF2 insulator layer 14 is arranged. 15 and 22 are arranged in the p-type GaAs epitaxial layer 12 and the InAs intermediate layer 13, and are a source region and a drain region in which Si is implanted. 16 and 17 are a source electrode and a drain electrode which are arranged so as to be linked with the source region 15 and the drain region 22, respectively. 18 is a gate electrode arranged on the CaF4 insulator layer 14. 19 is a channel region. As InAs is inserted into a GaAs/insulator boundary, Fermi level pinning phenomena caused by III-V compound semiconductor/insulator boundary level is effectively avoided. |
