| 摘要 |
PURPOSE:To attain high speed processing by providing an error correction code ECC calculation circuit so as to apply addition processing of an error correction code. CONSTITUTION:In sending data from a host system 1, the data is stored once in a buffer memory 2. When a write instruction is given from a microprocessor 6 and an address coincidence detection circuit 8 applies correspondence detection, the data in the memory 2 is read. An ECC calculation circuit 100 generates an error correction code from the data from the memory 2, the control data from a control data addition circuit 4 and the result of check from a cyclic redundancy check CRC calculation circuit 3. Through the constitution above, since the error correction code at the write of data to a recording medium is implemented at the same time with other processing, the entire processing time is reduced.
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